![]() Approach an optimal design independent of most layout considerations.ġ. ![]() Use the same MOSIS FET models specified in the PSpice input deck below. ![]() Using MoHAT and circuit simulation, design a custom non-inverting CMOS buffer to drive the load inverter shown in Fig. Figure 2 shows the layout of the same inverter, though minus the capacitor. Figure 1 shows the circuit diagram of the inverter your buffer will drive. The project consists of two parts: Schematic Design & Layout. The project aims to optimize circuit performance based on speed, power consumption, area, and figures of merit (FOM1 and FOM2) defined below. The project introduces design trade-offs in CMOS logic gate design. Figure 1 Inverter Load Schematic (Note: InvLoad in EE307W09.jelib doesn't have the 1 pF capacitor)
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